Memory segmentation is the division of computer's primary memory into segments or sections. In a computer system using segmentation, a reference to a memory location includes a value that identifies a segment and an offset within that segment. Segments or sections are also used in object files of compiled programs when they are linked together into a program image and when the image is loaded into memory.
Different segments may be created for different program modules, or for different classes of memory usage such as code and data segments. Certain segments may even be shared between programs.[1]
Hardware implementation
Memory segmentation is one method of implementing memory protection. Paging is another, and they can be combined. The size of a memory segment is generally not fixed and may be as small as a single byte.[2] Segments usually represent natural divisions of a program such as individual routines or data tables so segmentation is generally more visible to the programmer.[1]
A segment has a length and set of permissions associated with it. A process is only allowed to make a reference into a segment if the type of reference is allowed by the permissions, and the offset within the segment is within the range specified by the length of the segment. Otherwise, a hardware exception such as a segmentation fault is raised.
Information is also associated with a segment that indicates where the segment is located in memory. This might be the address of the first location in the segment, or the address of a page table for the segment if the segmentation is implemented with paging. In the first case, if a reference to a location within a segment is made, the offset within the segment will be added to address of the first location in the segment to give the address in memory of the referred-to item; in the second case, the offset of the segment is translated to a memory address using the page table.
Segments may also have a flag indicating whether the segment is present in main memory or not; if a segment is accessed that is not present in main memory, an exception is raised, and the operating system will read the segment into memory from secondary storage.
When a segment does not have a page table associated with it, the address of the first location in the segment is usually an address in main memory; in those situations, no paging is done. In the Intel 80386 and later, that address can either be an address in main memory, if paging is not enabled, or an address in a paged address space, if paging is enabled.
A memory management unit (MMU) is responsible for translating a segment and offset within that segment into a memory address, and for performing checks to make sure the translation can be done and that the reference to that segment and offset is permitted.
History
The Burroughs Corporation B5000 computer was one of the first to implement segmentation, and "perhaps the first commercial computer to provide virtual memory"[3] based on segmentation. The later B6500 computer also implemented segmentation; a version of its architecture is still in use today on the Unisys ClearPath Libra servers.
The GE-645 computer, a modification of the GE-635 with segmentation and paging support added, was designed in 1964 to support Multics.
The Intel iAPX 432,[4] begun in 1975, attempted to implement a true segmented architecture with memory protection on a microprocessor.
Prime, Stratus, Apollo, IBM System/38, and IBM AS/400 computers use memory segmentation.[5]
x86 architecture
Main article: x86 memory segmentation
The memory segmentation used by early x86 processors, beginning with the Intel 8086, does not provide any protection. Any program running on these processors can access any segment with no restrictions. A segment is only identified by its starting location; there is no length checking.
Segmentation in the Intel 80286 and later provides protection: with the introduction of the 80286, Intel retroactively named the sole operating mode of the previous x86 CPU models "real mode" and introduced a new "protected mode" with protection features. For backward compatibility, all x86 CPUs start in "real mode" with no memory protection, fixed 64 KiB segments, and only 20-bit (1024 KiB) addressing. An 80286 or later processor must be switched into another mode by software in order to use its full address space and advanced MMU features.
The x86-64 architecture does not use segmentation in long mode (64-bit mode). Four of the segment registers: CS, SS, DS, and ES are forced to 0, and the limit to 264. The segment registers FS and GS can still have a nonzero base address. This allows operating systems to use these segments for special purposes.
For instance, Microsoft Windows on x86-64 uses the GS segment to point to the Thread Environment Block, a small data structure for each thread, which contains information about exception handling, thread-local variables, and other per-thread state. Similarly, the Linux kernel uses the GS segment to store per-CPU data.
Object files
Segments or sections are also defined in object files. Segments in different object files may be combined by the linker according to rules specified when the segments are defined. Conventions exist for segments shared between object files; for instance, in DOS there are different memory models that specify the names of special segments and whether or not they may be combined.[6]
References
- ^ a b Englander, Irv (2003), The architecture of computer hardware and systems software (3rd ed.), Wiley, ISBN 0-471-07325-3
- ^ Intel Corporation (2012). Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3 (3A, 3B & 3C): System Programming Guide. pp. 3–13. http://download.intel.com/products/pr ocessor/manual/325384.pdf.
- ^ Mayer, Alastair J.W.. "The Architecture of the Burroughs B5000 - 20 Years Later and Still Ahead of the Times?". http://www.smecc.org/The%20Architectu re%20%20of%20the%20Burroughs%20B-5000 .htm. Retrieved March 15, 2012.
- ^ Intel Corporation (1981). Introduction to the IAPX 432 Architecture. pp. 78. http://www.bitsavers.org/pdf/intel/iA PX_432/171821-001_Introduction_to_the _iAPX_432_Architecture_Aug81.pdf.
- ^ Van Vleck, Thomas. "Multics General Info and FAQ". http://www.multicians.org/general.htm l. Retrieved March 18, 2012.
- ^ Irvine, Kip R. (1993), Assembly language for the IBM-PC (2nd ed.), New York: Macmillan, ISBN 0-02-359651-1
External links
- IA-32 Intel Architecture Software Developer’s Manual Volume 3A: System Programming Guide. http://www.intel.com/products/process or/manuals/index.htm.
- Operating Systems: Internals and Design Principles by William Stallings. Publisher: Prentice Hall. ISBN 0-13-147954-7. ISBN 978-0-13-147954-8.
See also
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| | | Manual memory management | |
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| | | Virtual memory | - Demand paging
- Page table
- Paging
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| | | Hardware | |
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| | | Garbage collection | |
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| | | Memory segmentation | |
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| | | Memory safety | |
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| | | Issues | |
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| | | Other | - Automatic variable
- International Symposium on Memory Management
- Region-based memory management
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