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Daftar/Tabel -- ARM microprocessor cores

This is a sub-article to ARM architecture.

ARM Holdings' microprocessor cores are listed here, sorted by generation release and name. ARM provides a summary of the numerous vendors who implement ARM cores in their design.[1] Keil also provides a somewhat newer summary of vendors of ARM based processors.[2] ARM further provides a chart[3] displaying an overview of the ARM processor lineup with performance and functionality versus capabilities for the more recent ARM7, ARM9, ARM11, Cortex-M, Cortex-R and Cortex-A device families.

ARM microprocessor cores

Designed by ARM

ARM FamilyARM ArchitectureARM CoreFeatureCache (I/D), MMUTypical MIPS @ MHz
ARM1ARMv1ARM1First implementationNone 
ARM2ARMv2ARM2ARMv2 added the MUL (multiply) instructionNone4 MIPS @ 8 MHz
0.33 DMIPS/MHz
ARMv2aARM250Integrated MEMC (MMU), Graphics and IO processor. ARMv2a added the SWP and SWPB (swap) instructions.None, MEMC1a7 MIPS @ 12 MHz
ARM3ARMv2aARM3First integrated memory cache.4 KB unified12 MIPS @ 25 MHz
0.50 DMIPS/MHz
ARM6ARMv3ARM60ARMv3 first to support 32-bit memory address space (previously 26-bit)None10 MIPS @ 12 MHz
ARM600As ARM60, cache and coprocessor bus (for FPA10 floating-point unit).4 KB unified28 MIPS @ 33 MHz
ARM610As ARM60, cache, no coprocessor bus.4 KB unified17 MIPS @ 20 MHz
0.65 DMIPS/MHz
ARM7ARMv3ARM700 8 KB unified40 MHz
ARM710As ARM700, no coprocessor bus.8 KB unified40 MHz
ARM710aAs ARM7108 KB unified40 MHz
0.68 DMIPS/MHz
ARM7TDMIARMv4TARM7TDMI(-S)3-stage pipeline, Thumbnone15 MIPS @ 16.8 MHz
63 DMIPS @ 70 MHz
ARM710TAs ARM7TDMI, cache8 KB unified, MMU36 MIPS @ 40 MHz
ARM720TAs ARM7TDMI, cache8 KB unified, MMU with Fast Context Switch Extension60 MIPS @ 59.8 MHz
ARM740TAs ARM7TDMI, cacheMPU 
ARM7EJARMv5TEJARM7EJ-S5-stage pipeline, Thumb, Jazelle DBX, Enhanced DSP instructionsnone 
ARM8ARMv4ARM810[4][5]5-stage pipeline, static branch prediction, double-bandwidth memory8 KB unified, MMU84 MIPS @ 72 MHz
1.16 DMIPS/MHz
ARM9TDMIARMv4TARM9TDMI5-stage pipeline, Thumbnone 
ARM920TAs ARM9TDMI, cache16 KB/16 KB, MMU with FCSE (Fast Context Switch Extension)[6]200 MIPS @ 180 MHz
ARM922TAs ARM9TDMI, caches8 KB/8 KB, MMU 
ARM940TAs ARM9TDMI, caches4 KB/4 KB, MPU 
ARM9EARMv5TEARM946E-SThumb, Enhanced DSP instructions, cachesvariable, tightly coupled memories, MPU 
ARM966E-SThumb, Enhanced DSP instructionsno cache, TCMs 
ARM968E-SAs ARM966E-Sno cache, TCMs 
ARMv5TEJARM926EJ-SThumb, Jazelle DBX, Enhanced DSP instructionsvariable, TCMs, MMU220 MIPS @ 200 MHz
ARMv5TEARM996HSClockless processor, as ARM966E-Sno caches, TCMs, MPU 
ARM10EARMv5TEARM1020E6-stage pipeline, Thumb, Enhanced DSP instructions, (VFP)32 KB/32 KB, MMU 
ARM1022EAs ARM1020E16 KB/16 KB, MMU 
ARMv5TEJARM1026EJ-SThumb, Jazelle DBX, Enhanced DSP instructions, (VFP)variable, MMU or MPU 
ARM11ARMv6ARM1136J(F)-S[7]8-stage pipeline, SIMD, Thumb, Jazelle DBX, (VFP), Enhanced DSP instructionsvariable, MMU740 @ 532–665 MHz (i.MX31 SoC), 400–528 MHz
ARMv6T2ARM1156T2(F)-S8-stage pipeline, SIMD, Thumb-2, (VFP), Enhanced DSP instructionsvariable, MPU 
ARMv6ZARM1176JZ(F)-SAs ARM1136EJ(F)-Svariable, MMU + TrustZone965 DMIPS @ 772 MHz, up to 2 600 DMIPS with four processors[8]
ARMv6KARM11 MPCoreAs ARM1136EJ(F)-S, 1–4 core SMPvariable, MMU 
SecureCoreARMv6-MSC000  0.9 DMIPS/MHz
ARMv4TSC100   
ARMv7-MSC300  1.25 DMIPS/MHz
Cortex-MARMv6-MCortex-M0 [9]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryNo cache, No TCM, No MPU0.84 DMIPS/MHz
Cortex-M0+ [11]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), optional system timer, optional bit-banding memoryNo cache, No TCM, optional MPU with 8 regions0.93 DMIPS/MHz
Cortex-M1 [12]Microcontroller profile, Thumb + Thumb-2 subset (BL, MRS, MSR, ISB, DSB, DMB),[10] hardware multiply instruction (optional small), OS option adds SVC / banked stack pointer, optional system timer, no bit-banding memoryNo cache, 0-1024 KB I-TCM, 0-1024 KB D-TCM, No MPU136 DMIPS @ 170 MHz,[13] (0.8 DMIPS/MHz FPGA-dependent)[14]
ARMv7-MCortex-M3 [15]Microcontroller profile, Thumb / Thumb-2, hardware multiply and divide instructions, optional bit-banding memoryNo cache, No TCM, optional MPU with 8 regions1.25 DMIPS/MHz
ARMv7E-MCortex-M4 [16]Microcontroller profile, Thumb / Thumb-2 / DSP / optional FPv4 single-precision FPU, hardware multiply and divide instructions, optional bit-banding memoryNo cache, No TCM, optional MPU with 8 regions1.25 DMIPS/MHz
Cortex-RARMv7-RCortex-R4 [17]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lockstep with fault logic0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 8/12 regions 
Cortex-R5 (MPCore) [18]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 8-stage pipeline dual-core running lock-step with fault logic / optional as 2 independent cores, low-latency peripheral port (LLPP), accelerator coherency port (ACP) [19]0-64 KB / 0-64 KB, 0-2 of 0-8 MB TCM, opt MPU with 12/16 regions 
Cortex-R7 (MPCore) [20]Real-time profile, Thumb / Thumb-2 / DSP / optional VFPv3 FPU and precision, hardware multiply and optional divide instructions, optional parity & ECC for internal buses / cache / TCM, 11-stage pipeline dual-core running lock-step with fault logic / out-of-order execution / dynamic register renaming / optional as 2 independent cores, low-latency peripheral port (LLPP), ACP [19]0-64 KB / 0-64 KB, ? of 0-128 KB TCM, opt MPU with 16 regions 
Cortex-AARMv7-ACortex-A5 [21]Application profile, ARM / Thumb / Thumb-2 / DSP / SIMD / Optional VFPv4-D16 FPU / Optional NEON / Jazelle RCT and DBX, 1–4 cores / optional MPCore, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)4-64 KB / 4-64 KB L1, MMU + TrustZone1.57 DMIPS / MHz per core
Cortex-A7 MPCore [22]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4-D16 FPU / NEON / Jazelle RCT and DBX / Hardware virtualization, in-order execution, superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, architecture and feature set are identical to A15, 8-10 stage pipeline, low-power design[23]32 KB / 32 KB L1, 0-4 MB L2, L1 & L2 have Parity & ECC, MMU + TrustZone1.9 DMIPS / MHz per core
Cortex-A8 [24]Application profile, ARM / Thumb / Thumb-2 / VFPv3 FPU / Optional NEON / Jazelle RCT and DAC, 13-stage superscalar pipeline16-32 KB / 16-32 KB L1, 0-1 MB L2 opt ECC, MMU + TrustZoneup to 2000 (2.0 DMIPS/MHz in speed from 600 MHz to greater than 1 GHz)
Cortex-A9 MPCore [25]Application profile, ARM / Thumb / Thumb-2 / DSP / Optional VFPv3 FPU / Optional NEON / Jazelle RCT and DBX, out-of-order speculative issue superscalar, 1–4 SMP cores, snoop control unit (SCU), generic interrupt controller (GIC), accelerator coherence port (ACP)16-64 KB / 16-64 KB L1, 0-8 MB L2 opt Parity, MMU + TrustZone2.5 DMIPS/MHz per core, 10,000 DMIPS @ 2 GHz on Performance Optimized TSMC 40G (dual core)
Cortex-A15 MPCore [26]Application profile, ARM / Thumb / Thumb-2 / DSP / VFPv4 FPU / NEON / Jazelle RCT / Hardware virtualization, out-of-order speculative issue superscalar, 1–4 SMP cores, Large Physical Address Extensions (LPAE), snoop control unit (SCU), generic interrupt controller (GIC), ACP, 15-24 stage pipeline[23]32 KB / 32 KB L1, 0-4 MB L2, L1 & L2 have Parity & ECC, MMU + TrustZoneAt least 3.5 DMIPS/MHz per core (Up to 4.01 DMIPS/MHz depending on implementation).[27]
Cortex-A50ARMv8-ACortex-A53[28]Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, dual issue, in-order pipeline8~64 KB/8~64 KB L1 per core, 128 KB~2 MB L2 shared, 40-bit physical addresses2.3 DMIPS/MHz
Cortex-A57[29]Application profile, AArch32 and AArch64, 1-4 SMP cores, Trustzone, NEON advanced SIMD, VFPv4, hardware virtualization, multi-issue, deeply out-of-order pipeline48 KB/32 KB L1 per core, 512 KB~2 MB L2 shared, 44-bit physical addressesAt least 4.1 DMIPS/MHz per core (Up to 4.76 DMIPS/MHz depending on implementation).
ARM FamilyARM ArchitectureARM CoreFeatureCache (I/D), MMUTypical MIPS @ MHz

Designed by third parties

These cores implement the ARM instruction set, and were developed independently by companies with an architectural license from ARM.

FamilyARM ArchitectureCoreFeatureCache (I/D), MMUTypical MIPS @ MHz
StrongARMARMv4SA-15-stage pipeline16 KB/8–16 KB, MMU133–206 MHz
1.0 DMIPS/MHz
Faraday[30]ARMv4FA5106-stage pipelineup to 32 KB / 32 KB Cache, MPU1.26 DMIPS/MHz
100-200 MHz
FA526up to 32 KB / 32 KB Cache, MMU1.26 MIPS/MHz
166-300 MHz
FA6268-stage pipeline32 KB/32 KB Cache, MMU1.35 DMIPS/MHz
500 MHz
ARMv5TEFA606TE5-stage pipelineno cache, no MMU1.22 DMIPS/MHz
200 MHz
FA626TE8-stage pipeline32 KB/32 KB Cache, MMU1.43 MIPS/MHz
800 MHz
FMP626TE8-stage pipeline, SMP1.43 MIPS/MHz
500 MHz
FA726TE13 stage pipeline, dual issue2.4 DMIPS/MHz
1000 MHz
XScaleARMv5TEXScale7-stage pipeline, Thumb, Enhanced DSP instructions32 KB/32 KB, MMU133–400 MHz
BulverdeWireless MMX, Wireless SpeedStep added32 KB/32 KB, MMU312–624 MHz
Monahans[31]Wireless MMX2 added32 KB/32 KB (L1), optional L2 cache up to 512 KB, MMUup to 1.25 GHz
SheevaARMv5Feroceon5-8 stage pipeline, single-issue16 KB / 16 KB, MMU600-2000 MHz
Jolteon5-8 stage pipeline, dual-issue32 KB / 32 KB, MMU
PJ1 (Mohawk)5-8 stage pipeline, single-issue, Wireless MMX232 KB / 32 KB, MMU1.46 DMIPS/MHz
1.06 GHz
ARMv6/ARMv7-APJ46-9 stage pipeline, dual-issue, Wireless MMX2, SMP32 KB / 32 KB, MMU2.41 DMIPS/MHz
1.6 GHz
SnapdragonARMv7-AScorpion [32]Used by some members of the Snapdragon S1, S2, and S3 families. 1 or 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv3 FPU / NEON (128-bit wide)256 KB L2 per core2.1 DMIPS / MHz per core
Krait [32]Used by some members of the Snapdragon S4 family. 1, 2, or 4 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEON (128-bit wide)4 KB / 4 KB L0, 16 KB / 16 KB L1, 512 KB L2 per core3.3 DMIPS / MHz per core
Apple AxARMv7-AApple Swift [33]Custom ARM core used in the Apple A6 and Apple A6X. 2 cores. ARM / Thumb / Thumb-2 / DSP / SIMD / VFPv4 FPU / NEONL1: 32 kB instruction + 32 kB data, L2: 1 MB3.5 DMIPS / MHz Per Core
X-GeneARMv8-AX-Gene64 bit, quad issue, SMPCache, MMU, Virtualization3 GHz
DenverARMv8-A 64 bit  

See also

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Portal iconElectronics portal

References

  1. ^ "Line Card" (PDF). 2003. Retrieved 2011-01-06. 
  2. ^ ARM Ltd and ARM Germany GmbH. "Device Database". Keil. Retrieved 2011-01-06. 
  3. ^ "Processors". ARM. 2011. Retrieved 2011-01-06. 
  4. ^ ARM Holdings (1996-08-07) (PDF), ARM810 – Dancing to the Beat of a Different Drum, Hot Chips, http://www.dlhoffman.com/publiclibrar y/software/hot_chips_papers/hc96/hc8_ pdf/4.1.pdf.
  5. ^ "VLSI Technology Now Shipping ARM810". EE Times. August 26, 1996. Retrieved March 16, 2012. 
  6. ^ Register 13, FCSE PID register ARM920T Technical Reference Manual
  7. ^ "ARM1136J(F)-S – ARM Processor". Arm.com. Retrieved 2009-04-18. 
  8. ^ "ARM11 Processor Family". ARM. Retrieved 2010-12-13. 
  9. ^ Cortex-M0 Specification Summary; ARM Holdings.
  10. ^ a b c Cortex-M0/M0+/M1 Instruction Set; ARM Holding.
  11. ^ Cortex-M0+ Specification Summary; ARM Holdings.
  12. ^ Cortex-M1 Specification Summary; ARM Holdings.
  13. ^ "ARM Extends Cortex Family with First Processor Optimized for FPGA", ARM press release, March 19, 2007. Retrieved April 11, 2007.
  14. ^ "ARM Cortex-M1", ARM product website. Retrieved April 11, 2007.
  15. ^ Cortex-M3 Specification Summary; ARM Holdings.
  16. ^ Cortex-M4 Specification Summary; ARM Holdings.
  17. ^ Cortex-R4 Specification Summary; ARM Holdings.
  18. ^ Cortex-R5 Specification Summary; ARM Holdings.
  19. ^ a b Cortex-R5 & Cortex-R7 Press Release; ARM Holdings; January 31, 2011.
  20. ^ Cortex-R7 Specification Summary; ARM Holdings.
  21. ^ Cortex-A5 Specification Summary; ARM Holdings.
  22. ^ Cortex-A7 Specification Summary; ARM Holdings.
  23. ^ a b Deep inside ARM's new Intel killer; The Register; October 20, 2011.
  24. ^ Cortex-A8 Specification Summary; ARM Holdings.
  25. ^ Cortex-A9 Specification Summary; ARM Holdings.
  26. ^ Cortex-A15 Specification Summary; ARM Holdings.
  27. ^ Exclusive : ARM Cortex-A15 "40 Per Cent" Faster Than Cortex-A9 | ITProPortal.com
  28. ^ "Cortex-A53 Processor". ARM Holdings. Retrieved 2012-10-13. 
  29. ^ "Cortex-A57 Processor". ARM Holdings. Retrieved 2012-10-13. 
  30. ^ [1]
  31. ^ "3rd Generation Intel XScale Microarchitecture: Developer’s Manual". download.intel.com. Intel. May 2007. Retrieved 2 December 2010. 
  32. ^ a b Qualcomm's New Snapdragon S4: MSM8960 & Krait Architecture Explored; Anandtech.
  33. ^ Lal Shimpi, Anand (September 15, 2012). "The iPhone 5's A6 SoC: Not A15 or A9, a Custom Apple Core Instead". AnandTech. Retrieved September 15, 2012. 

Further reading

  • The Definitive Guide to the ARM Cortex-M0; 1st Edition; Joseph Yiu; Newnes; 552 pages; 2011; ISBN 978-0-12-385477-3. (Online Sample)
  • The Definitive Guide to the ARM Cortex-M3; 2nd Edition; Joseph Yiu; Newnes; 480 pages; 2009; ISBN 978-1-85617-963-8. (Online Sample)



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