Hexagon is a DSP based CPU architecture developed by Qualcomm. It uses VLIW and is capable of dispatching up to 4 instructions to 4 Execution Units every clock.[1][2]
The Hexagon architecture is designed to deliver performance with low power over a variety of applications. It has features such as multithreading, privilege levels, VLIW, SIMD,[3] and instructions geared toward efficient signal processing. The port of Linux for Hexagon runs under a hypervisor layer and was merged with the 3.2 release of the kernel.[4][5] Support for Hexagon was added in 3.1 release of LLVM by Tony Linthicum.[6] There is also a non-FSF maintained branch of GCC.[7]
Hexagon DSPs are included in Snapdragon SoC since 2006.[8] In Snapdragon S4 (MSM8960 and newer) there are three Hexagon cores, two in the Modem subsystem and one in the Multimedia subsystem.
They are also used in some femtocell processors of Qualcomm, including FSM9832.[9]
There are four generations of DSP architecture: H1 (2006), H2 (2007-2008), H3 (2009), H4 (2010-2011). H4 has 20 DMIPS per milliwatt, works with frequency 500 MHz.[8] Clock speed of Hexagon varies in 400-600 MHz for QDSP6 and in 256-350 MHz for QDSP5.[10]
Code sample
This is a single instruction packet from the inner loop of a FFT:[2]
{ R17:16 = MEMD(R0++M1) MEMD(R6++M1) = R25:24 R20 = CMPY(R20, R8):<<1:rnd:sat R11:10 = VADDH(R11:10, R13:12)}:endloop0This packet is claimed to be equal to 29 classic RISC operations; it includes vector add (4x 16bit), complex multiply operation and hardware loop support. All instructions of the packet are done in the same cycle.
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