LatticeMico32| Designer | Lattice Semiconductor |
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| Bits | 32 |
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| Introduced | 2006 |
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| Design | RISC |
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| Type | Register-Register |
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| Encoding | Fixed 32-bit |
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| Branching | Compare and branch |
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| Endianness | Big |
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| Extensions | User-defined |
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| Open | Yes |
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| Registers |
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| General purpose | 32 |
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LatticeMico32 is a 32-bit microprocessor soft core from Lattice Semiconductor optimized for field-programmable gate arrays (FPGAs). It uses a Harvard architecture, which means the instruction and data buses are separate. Bus arbitration logic can be used to combine the two buses, if desired.
LatticeMico32 is licensed under an open intellectual property (IP) core license. This means that the Mico32 is not restricted to Lattice FPGAs, and can be legally used on any host architecture (FPGA, ASIC, or software emulation). It is possible to embed a LatticeMico32 core into Xilinx and Altera FPGAs, in addition to the Lattice parts the LatticeMico32 was developed for.
Both the CPU core and the development toolchain are available in source-code form, allowing third-parties to implement changes to the processor architecture.
Features
- RISC load/store architecture.
- 32-bit data path.
- 32-bit fixed-size instructions (all instructions are 32 bits, including jump, call and branch instructions).
- 32 general purpose registers (R0 is typically set to zero by convention, however R0 is a standard register and other values may be assigned to it if so desired).
- Up to 32 external interrupts.
- Configurable instruction set including user defined instructions.
- Optional configurable caches (direct-mapped or 2-way set-associative, with a variety of cache sizes and arrangements).
- Optional pipelined memories.
- Dual Wishbone memory interfaces (one read-only instruction bus, one read-write data/peripheral bus).
- Memory mapped I/O.
- 6 stage pipeline.
Toolchain
See also
External links
RISC-based processor architectures |
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