eSi-RISC| Designer | EnSilica |
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| Bits | 16/32 |
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| Introduced | 2009 |
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| Design | RISC |
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| Type | Register-Register |
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| Encoding | Intermixed 16 and 32-bit |
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| Branching | Compare and branch and condition code |
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| Endianness | Big or little |
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| Extensions | User-defined instructions |
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| Registers |
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| 8/16/32 General Purpose, 8/16/32 Vector |
eSi-RISC is a configurable CPU architecture from EnSilica. It is currently available in three different implementations: the eSi-1600, eSi-3200 and eSi-3250.[1] The eSi-1600 features a 16-bit data-path, while the eSi-3200 and eSi-3250 feature 32-bit data-paths. Each of these processors are licensed as soft IP cores, suitable for integrating in to both ASICs and FPGAs.[2]
Architecture
The main features of the eSi-RISC architecture are as follows:
eSi-3250 SoC architecture.
- RISC-like load/store architecture.
- Configurable 16 or 32-bit data-path.
- Instructions are encoded in either 16 or 32-bits.
- 8, 16 or 32 general purpose registers.
- 0, 8, 16 or 32 vector registers.
- 0 to 8 accumulators.
- Up to 32 external interrupts.
- Configurable instruction set including support for integer, floating-point and fixed-point arithmetic.
- Optional support for user-defined instructions.
- Optional caches (Configurable size and associtivity).
- Optional MMU supporting both memory protection and dynamic address translation.
- AMBA AXI, AHB and APB bus interfaces.
- Memory mapped I/O.
- 5-stage pipeline.
- Hardware JTAG debug.
While there are many different 16 or 32-bit Soft microprocessor IP cores available, eSi-RISC is the only architecture licensed as an IP core that has both 16 and 32-bit implementations.
Unlike in other RISC architectures supporting both 16 and 32-bit instructions, such as ARM/Thumb or MIPS/MIPS-16, 16 and 32-bit instructions in the eSi-RISC architecture can be freely intermixed, rather than having different modes where you are executing either all 16-bit instructions or all 32-bit instructions. This helps improve code density without compromising performance. The 16-bit instructions support two register operands in the lower 16 registers, whereas the 32-bit instructions support three register operands and access to all 32 registers.
eSi-RISC includes support for Multiprocessing. Implementations have included up to seven eSi-3250's on a single chip.[3]
Toolchain
The eSi-RISC toolchain is based on combination of a port of the GNU toolchain and the Eclipse IDE.[4] This includes:
- GCC - C/C++ compiler.
- Binutils - Assembler, linker and binary utilities.
- GDB - Debugger.
- Eclipse - Integrated Development Environment.
The C library is Newlib and the C++ library is Libstdc++. Ported RTOSes include MicroC/OS-II, FreeRTOS, ERIKA Enterprise [5] and Phoenix-RTOS [6]
References
- ^ [1] Electronics Weekly, 17 November 2009
- ^ [2] EE Times, 17 November 2009
- ^ [3] Design & Reuse, 2011
- ^ [4] EnSilica, 2009
- ^ [5] Electronics Weekly, 2010,
- ^ [6] Cambridge Network 2013
External links
RISC-based processor architectures |
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