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OpenRISC

OpenRISC
DesignerOpenCores community
Bits32, 64
DesignRISC
EncodingFixed
OpenYes
Registers
General purpose16 or 32
Floating pointOptional

OpenRISC is the original flagship project of the OpenCores community. This project aims to develop a series of general purpose open source RISC CPU architectures. The first (and currently only) architectural description is for the OpenRISC 1000, describing a family of 32 and 64-bit processors with optional floating point and vector processing support.[1]

A team from OpenCores provided the first implementation, the OpenRISC 1200, written in the Verilog hardware description language. The hardware design was released under the GNU Lesser General Public License (LGPL), while the models and firmware were released under the GNU General Public License (GPL). A reference SoC implementation based on the OpenRISC 1200 was developed, known as ORPSoC (the OpenRISC Reference Platform System-on-Chip). A number of groups demonstrated ORPSoC and other OR1200 based designs running on FPGA.[2][3]

Contents

Instruction set

The instruction set is a reasonably simple example of a modern RISC using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32 and 64 bit versions of the specification, the main difference being the register width (32 or 64 bits) and pagetable layout. The OpenRISC specification includes all features common to modern desktop/server processors: a supervisor mode and virtual memory system, optional read, write and execute control for memory pages, and instructions for synchronization and interrupt handling between multiple processors.

As of October 2011, there are still some minor details in the 64-bit specification that are incomplete or ambiguous.

Another notable feature is a rich set of SIMD instructions intended for digital signal processing.

Implementations

Most implementations are on FPGAs which give the possibility to iterate on the design at the cost of performance.

As the OpenRISC 1000 is now considered stable the OpenCores project is trying to build a cost-efficient ASIC with this design to get improved performance.[4] They launched a call for donations in 2011 with the aim to produce the first ASIC in Q1 2012.[5] As of July 2012, the first ASIC hasn't been produced yet.

Commercial implementations

Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC (who also maintain the opencores.org website) and the BA12, BA14 and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE FPGA prototyping board, which is capable of running both the OpenRISC 1000 and BA12. Flextronics International and Jennic Limited manufactured the OpenRISC as part of an ASIC. Samsung use the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series).[6]

Cadence Design Systems have started using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to Accellera[7]).

TechEdSat, the first NASA OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.[8][9]

Academic and non-commercial use

Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example Stefan Wallentowitz and his team at the Institute for Integrated Systems at the Technical University Munich have used OpenRISC in research into multicore architectures.[10] The Open Source Hardware User Group in the UK has on two occasions[11][12] run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,[13] which attracted the interest of EE Times.[14]

Toolchain support

The OpenCores community have ported the GNU toolchain to OpenRISC to support development in C and C++. Using this toolchain the newlib and uClibc libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical development environment based on this toolchain. A project to port LLVM to the OpenRISC 1000 architecture started in early 2012 (project wiki page).

The OR1K project provides an instruction set simulator, or1ksim. The flagship implementation, the OR1200, is an RTL model in Verilog HDL, from which a SystemC-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative set up by Imperas.

Operating system support

Linux support

Support for the mainline Linux kernel was gained in version 3.1.[15] The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).[16] Previously OpenRISC 1000 architecture, but this has now been superseded by the mainline port.

QEMU support

Since version 1.2 [17] QEMU supports emulating OpenRISC platforms.

RTOS support

A number of real-time operating systems have been ported to OpenRISC, including RTEMS, FreeRTOS and eCos.

See also

Portal iconFree software portal

References

  1. ^ Damjan Lampret et al., "OpenRISC 1000 Architecture Manual", Rev 1.3, 15 Nov 2007. Available from the OpenCores website [1]
  2. ^ Patrick Pelgrims, Tom Tierens and Dries Driessens, "Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGA’s", De Nayer Instituut, Hogeschool voor Wetenschap & Kunst, 2004. Available online [2]
  3. ^ Xiang Li and Lin Zuo, "Open source embedded platform based on OpenRISC and DE2-70", Masters dissertation, SoC program, KTH, Sweden. Available online [3]
  4. ^ OpenCores - Call for OpenRISC ASIC donations
  5. ^ OpenCores donation FAQ
  6. ^ Samsung Open Source Release Center, follow the links → TV & VIDEO → TV → DTV → ETC → OR1200.zip
  7. ^ UVM Reference Flow, Accellera website (undated).
  8. ^ Post to the openrisc mailing lists at lists.opencores.org and lists.openrisc.net on 8 April 2012 by Fredrick Bruhn, CEO of ÅAC Microtec
  9. ^ Press release 11 October 2012, ÅAC Microtec AB.
  10. ^ [www.lis.ei.tum.de/fileadmin/w00bdv/. ../ACACES2010_Poster.pdf Multicore Architecture and Programming Model Co-Optimization (MAPCO)], Stefan Wallentowitz, Thomas Wild and Andreas Herkersdorf. Research poster atthe Sixth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), Terrassa (Barcelona), Spain, 11–17 July 2010.
  11. ^ Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000). OSHUG meeting #9, Skills Matter, 116-120 Goswell Road, London, 21 April 2011.
  12. ^ Practical System-on-Chip (Program your own open source FPGA SoC). OSHUG meeting #17, Centre for Creative Collaboration, 16 Acton Street, London, 29 March 2012.
  13. ^ OpenRISC 1200 soft processor. Blog post by Sven-Åke Andersson, 2 March 2012.
  14. ^ Comparing four 32-bit soft processor cores. Clive Maxfield, EE Times, 3 May 2012.
  15. ^ "git.kernel.org - linux/kernel/git/torvalds/linux-2.6.g it/tree - arch/openrisc/". git.kernel.org. Retrieved 2011-10-17. 
  16. ^ "Linux 3.1". Kernel Newbies. Retrieved 2011-10-17. 
  17. ^ QEMU Changelog 1.2

External links

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